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Multimedia ICs
NTSC / PAL digital RGB encoder
BU1424K
The BU1424K is an IC that converts digital RGB / YUV input to composite (NTSC / PAL / PAL60), luminance (Y), and chrominance (C) signals, and outputs the results.
*Applications for VIDEO-CDs and CD-G decoders Video interfaces *Features supported. 1) Input clocks
27.0 / 13.5MHz 28.636 / 14.318MHz 28.375 / 14.1875MHz 35.4695 / 17.73475MHz 2) 24-bit RGB and 16-bit YUV input signals are supported. 3) Both master and slave systems are supported. 4) 9-bit high-speed DAC is used for DAC output of composite VIDEO, Y, and C signals. 5) Internal 8-color OSD output function is provided. 6) FSC-TRAP on the Y channel can be turned on and off. 7) C channel is equipped with an internal chrominance band-pass filter in addition to the U,V. low-pass filter. 8) 5V single power supply, low power consumption. (0.4W typ.) 9) Y and C output can be turned off (the power consumption with Y and C off is 0.25W typ.).
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Multimedia ICs
BU1424K
*Block diagram
OSDSW BOSD GOSD ROSD
RGB 24BITS OSD PALLET
RD GD / Y BD / UV
LATCH
RGB to YUV UV FILTER
Y-LEVEL SHIFT CHROMA GEN
Y-FILTER
MIX SIG and sync burst
DAC V Y C
VOUT YOUT COUT
C-FILTER
VOLK RSTB VIDEO TIMING CONTROL PIXCLK SYNC BLANK HSY SUB CARRIER BURST GENERATOR BURST VSY BCLK MODE CONTROL FIELD / FLAME CONTROL
YFILONB [1.0]
CDGSWB
TEST1,2
PAL60B
2
CLKSW
IM [0.1]
G4FSC
ADDH
NTB
INT
Multimedia ICs
BU1424K
*Pin descriptions
Pin No. Pin name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 BOSD GD0 / Y0 GD1 / Y1 GD2 / Y2 GD3 / Y3 GD4 / Y4 GD5 / Y5 GD6 / Y6 GND GD7 / Y7 Function OSD BLUE DATA INPUT GREEN DATA Bit0 (LSB) GREEN DATA Bit1 GREEN DATA Bit2 GREEN DATA Bit3 GREEN DATA Bit4 GREEN DATA Bit5 GREEN DATA Bit6 DIGITAL GROUND GREEN DATA Bit7 (MSB) Pin No. Pin name Function SELECT MASTER / SLAVE + 0.5 / - 0.5LINE at NON-INTER DAC BIAS CHROMA OUTPUT GROUND CHROMA OUTPUT Composite Output Ground COMPOSITE OUTPUT Analog Ground (DAC. VREF) ANALOG (DAC) VDD REFERENCE RESISTOR ANALOG (VREF) VDD Luminance Output Ground Luminance Output 4FSC / 3.2FSC at PALCD-G
1
33 34 35 36 37 38 39 40 41 42 43 44 45 46
SLABEB ADDH VREF-C CGND COUT VGND VOUT AVSS AVDD IR AVDD YGND YOUT C4FSC
1 1
BD0 / UV0 BLUE DATA Bit0 (LSB) BD1 / UV1 BLUE DATA Bit1 BD2 / UV2 BLUE DATA Bit2 BD3 / UV3 BLUE DATA Bit3 OSDSW OSD ENABLE / DISABLE
1
47 48 49 50 51 52 53 54
YFILON2B Y-FILSEL THROU / FILON2 YCOFF DAC (YOUT. COUT) OFF
CDGSWB SELECT Video-CD / CD-G BD4 / UV4 BLUE DATA Bit4 BD5 / UV5 BLUE DATA Bit5 BD6 / UV6 BLUE DATA Bit6 BD7 / UV7 BLUE DATA Bit7 (MSB) GND NTB IM0 IM1 TEST1 TEST2 VSY HSY PIXCLK BCLK VDD INT DIGITAL GROUND SELECT NTSC / PAL MODE SELECT YUV / RGB SELECT DAC / NORMAL Normally pull down to GND SELECT U / V TIMING V-SYNC INPUT or OUTPUT H-SYNC INPUT or OUTPUT 1 / 2freq. of BCLK INTERNAL CLOCK OUTPUT DIGITAL VDD Interlace / Non-Interlace
YFILON1B Y-FILSEL THROU / FILON1 PAL60B VCLK RSTB CLKSW RD0 RD1 RD2 ROSD RD3 RD4 RD5 VDD RD6 RD7 GOSD NORMAL / PAL60 at PALMODE Video Clock Input NORMAL / RESET SEL x 1CLK / x 2CLK RED DATA Bit0 (LSB) RED DATA Bit1 RED DATA Bit2 OSD RED DATA INPUT RED DATA Bit3 RED DATA Bit4 RED DATA Bit5 DIGITAL VDD RED DATA Bit6 RED DATA Bit7 OSD GREEN DATA INPUT
1 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 1 1 1
55 56 57 58 59 60 61 62 63 64
1 Internal pull-down resistor 2 Internal pull-up resistor
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Multimedia ICs
BU1424K
*Absolute maximum ratings (Ta = 25C)
Parameter Applied voltage Input voltage Storage temperature Power dissipation Symbol VDD, AVDD VIN Tstg Pd Limits - 0.5 ~ + 7.0 - 0.5 ~ VDD + 0.5 - 55 ~ + 150 13501 Unit V V C mW
1 Reduced by 11mW for each increase in Ta of 1C over 25C. Operation is not guaranteed at this value.
Not designed for radiation resistance.
When mounted on a 120mm x 140mm x 1.0mm glass epoxy board.
*Recommended operating conditions (Ta = 25C)
Parameter Power supply voltage Input high level voltage Input low level voltage Analog input voltage Operating temperature Symbol VDD = AVDD VIH VIL VAIN Topr Limits + 4.75 ~ + 5.25 + 2.1 ~ VDD 0 ~ + 0.8 0 ~ AVDD - 25 ~ + 60 Unit V V V V C
Should be used at VDD = AVDD.
*Electrical characteristics (unless otherwise noted, Ta = 25C, VDD = AVDD = 5.0V, GND = AVSS = VGND = CGND = YGND)
Digital block
Parameter Burst frequency 1 Burst frequency 2 Burst cycle Operating circuit current 1 Operating circuit current 2 Output high level voltage Output low level voltage Input high level voltage Input low level voltage Input high level current Input low level current Symbol fBST1 fBST2 CBST Idd1 Idd2 VOH VOL VIH VIL IIH IIL Min. -- -- -- -- -- 4.0 -- 2.1 -- - 10 - 10 Typ. 3.57954 4.43361 9 80 40 4.5 0.5 -- -- 0.0 0.0 Max. -- -- -- -- -- -- 1.0 -- 0.8 10.0 10.0 Unit MHz MHz CYC mA mA V V V V A A 27MHz color bar 27MHz color bar PD mode IOH = - 2.0mA IOH = 2.0mA -- -- -- -- Conditions -- -- --
DAC block
Parameter DAC resolution Linearity error Y white level current Y black level current Y zero level current V white level current V black level current V zero level current Symbol RES EL IYW IYB IYZ IYW IYB IYZ Min. -- -- -- -- - 10 -- -- - 10 Typ. 9 0.5 25.14 7.24 0.0 25.14 7.24 0.0 Max. -- 3.0 -- -- 10.0 -- -- 10.0 Unit BITS LSB mA mA A mA mA A IR = 1.2k -- -- -- -- -- -- Conditions --
4
Y-filter select Pixel Clock in Reset [Low active] in
6 7
3 4 5
0 1 2
R Data 0...7 G Data 0...7 B Data 0...7
Multimedia ICs
OSD in
[Red] OSD in [Green] [Blue] OSD in OSD enable
64 55 54 53 52 51 50 49
63
62
61
60
59
58
57
56
Luminance 75 YCOFF
48 47 46 45 44 43 42 41 40 39 38 37
YFILON1B PAL GOB VCLK RSTB CLKSW RD0 RD1 RD2 ROSD RD3 RD4 RD5 VDD RD6 RD7 GOSD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
BOSD GD0 GD1 GD2 GD3 GD4 GD5 GD6 GND GD7 BD0 BD1 BD2 BD3 OSDSW CDGSWB INT VDD BCLK PIXCLK HSY VSY TEST2 TEST1 IM1 IM0 NTB GND BD7 BD6 BD5 BD4 VOUT VGND COUT CGND VREF ADDH SLABEB AVSS AVDD IR AVDD YGND YOUT G4FSC YFILON2B
012
3
Composite 1.2k 75
4
56
BU1424K
*Applicationinexample mode: Doubled clock is input and 24-bit RGB input is used (1) Example Master
Fig.1
36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
7
012
Chrominance 75 0.01F
3
Video-CD / CD-C
7 6 5 4
OSD CLOCK
PAL / NTSC Hsync out Vsync out
BU1424K
INTERLACE / NON-INTER
5
(2) Example in Slave mode: Doubled clock is input and 16-bit YUV input is used
6
Y-filter select Pixel Clock in Reset [Low active] in 6 7 3 4 5 0 1 2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Y Data 0...7 U.V Data 0...7
Multimedia ICs
OSD in
[Red] OSD in [Green] [Blue] OSD in OSD enable
Luminance 75 YCOFF
48 47 46 45 44 43 42 41 40 39 38 37
YFILON1B PALGOB YCLK RSTB CLKSW RD0 RD1 RD2 ROSD RD3 RD4 RD5 VDD RD6 RD7 GOSD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
BOSD GD0 GD1 G4FSC YOUT YGND AVDD IR AVDD AVSS VOUT VGND COUT CGND VREF ADDH SLABEB GD2 GD3 GD4 GD5 GD6 GND GD7 BD0 BD1 BD2 BD3 OSDSW CDGSWB INT VDD BCLK PIXCLK HSY VSY TEST2 TEST1 IM1 IM0 NTB GND BD7 BD6 BD5 BD4 YFILON2B
012 1.2k
3
Composite 75
4
56
BU1424K
Fig.2
36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
7
012
Chrominance 75 0.01F
3
Video-CD / CD-C
7 6 5 4
OSD CLOCK
PAL / NTSC INTERLACE / NON-INTER Vsync in Hsync in
BU1424K
Multimedia ICs
BU1424K
*Equivalent circuits
Pin No. Pin name I/O Equivalent circuit Function 2~8 10 GD (7: 0) I G data input pin for 24-bit RGB input. Y data input pin for 16-bit YUV input.
11 ~ 14 17 ~ 20
BD (7: 0)
I
B data input pin for 24-bit RGB input. U, V data input pins for 16-bit YUV input.
54 ~ 56 58 ~ 60 62.63
RD (7: 0)
I
R data input pin for 24-bit RGB input.
1 57 64 15
ROSD GOSD BOSD OSDSW
I
OSD data input pin when using the OSD function. When the OSDSW pin is HIGH, input to the ROSD, GOSD, and BOSD pins takes precedence over RGB, and the data is converted.
23 24
IM0 IM1
I
Control pins used to select RGB (24bit), YUV (16-bit) or DAC Through as the input mode.
16
CDGSWB
I
Switches the mode between VideoCD (HIGH) and CD-G (LOW).
22
NTB
I
Switches the mode between NTSC (LOW) and PAL (HIGH).
28
HSY
I/O
This is the horizontal synchronization signal pin. Negative polarity HSYNC signals are input (when SLABEB = LOW) or output (when SLABEB = HIGH) here. This is also used as the synchronization signal for fixing the PIXCLK output phase.
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Multimedia ICs
BU1424K
Pin No.
Pin name
I/O
Equivalent circuit
Function
27
VSY
I
Vertical synchronization signals (VSYNC) are input (when SLABEB = LOW) or output (when SLABEB = HIGH) here.
29
PIXCLK
O
The internal processing clock is divided in half and then output. Data is read at the point at which the edge of this clock changes. This can also be used as the clock for the OSD IC.
32
INT
I
This pin switches between interlace (when HIGH) and non-interlace (when LOW) modes. This pin is effective in both the VIDEO-CD and CD-G modes.
33 34
SLABEB ADDH
I I
This pin switches between the Master (when HIGH) and Slave (when LOW) modes. It is effective in the noninterlace mode, and it switches between - 0.5 lines (when LOW) and + 0.5 lines (when HIGH) for the number of lines in an interlace field.
35
Vref-C
I
This is the reference voltage generator circuit monitoring pin which determines the output amplitude (output current for 1 LSB) of the DAC.
8
Multimedia ICs
BU1424K
Pin No.
Pin name
I/O
Equivalent circuit
Function
37
COUT
O
This is the chrominance output pin for the S pin.
39
VOUT
O
Composite output pin.
45
YOUT
O
Luminance output pin for the S pin.
42
IR
I
The output amplitude (output current for 1 LSB) of the DAC is specified using an external resistor, and this pin controls the value of the current flowing per bit.
48
YCOFF
I
When there is HIGH input at the signal input pin, which switches to and from the low power consumption mode, this turns off the output from the YOUT and COUT pins.
30
BCLK
O
Output for the internal clock. When CLKSW is HIGH, the VCLK buffer output. When CLKSW is LOW, the VCLK 1 / 2 cycle output.
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Multimedia ICs
BU1424K
Pin No.
Pin name
I/O
Equivalent circuit
Function
51
VCLK
I
Input pin for the reference clock in the Video-CD mode.
52
RSTB
I
Reset input pin which initializes the system.
49
YFILON1B YFILON2B
I
Selects the F characteristic of the Y-FILTER. However, this is only effective when OSDSW is LOW.
50
PAL60B
I
Switches between the PAL and PAL60 modes. This is effective only when the NTB pin is HIGH. (PAL mode only).
53
CLKSW
I
This switches between dividing the VCLK input in half and using it as an internal clock (when LOW), and using it as an internal clock without dividing it in half (when HIGH).
46
G4FSC
I
Switching pin for CDG mode input frequency 14.1875 / 4fsc.
25 26
TEST1 TEST2
I
Normally, this is connected to the GND pin. However, when 16-bit YUV input is used, the TEST2 pin can be used as the U and V timing control pins.
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Multimedia ICs
BU1424K
Pin No.
Pin name
I/O
Equivalent circuit
Function
31 61 41 43
VDD AVDD
--
--
Power supply pin for the digital, the analog and blocks.
9 21 36 38 40 44
GND CGND VGND AVSS YGND
--
--
Ground for digital and analog blocks.
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Multimedia ICs
BU1424K
*Circuit operation (1) Overview
The BU1424K converts digital images and video data with an 8-bit configuration to 9-bit composite signals (VOUT), luminance signals (YOUT), and chrominance signals (COUT) for the NTSC, PAL, and PAL60 formats, and outputs the converted data as analog TV signals. The user may select whether VOUT consists of chrominance signals that have passed through a chrominance band pass and luminance signals that have been mixed, or luminance signals that have passed through a chrominance trap and luminance signals that have not passed through a chrominance trap. The F characteristic of this chrominance trap may be selected from among three available types. Since YOUT normally does not pass through the trap, it is optimum for the S pin. COUT normally passes through the chrominance band pass, and is thus highly resistance to dot interference. In addition, when used in the doubled clock mode, it passes through an interpolator filter, and for that reason is able to reproduce even cleaner image quality. A correspondence can be set up between input digital image data and Video-CD and CD-G decoder output. Output TV signals, in addition to switching among the NTSC, PAL, and PAL60 modes, can be switched between the interlace and non-interlace modes. The data clock input to the VCLK pin can also be input as a doubled clock for the data rate (in doubled clock modes). In doubled clock modes, data is read and processed at the rising edge of an internal clock that has been divided in half. In ordinary clock modes, data is read and processed at the rising edge of the clock that has the same phase as the input clock. Two input data formats are supported: 24-bit RGB (4: 4: 4) and 16-bit YUV (4: 2: 2). These are input to RD0 to 7, GD0 to 7, and BD0 to 7, respectively. The selected input format can be switched using the IM0 and IM1 pin input. When the OSDSW pin is set to the "Enabled" (H) state, data input to the ROSD, GOSD, and BOSD pins becomes effective, making it possible to input 7-color (8 Table 1: Low power consumption mode with the YCOFF pin
Pin No. Pin name YCOFF 48 LOW HIGH VOUT pin Composite signal Composite signal
including black) chrominance data. At the same time, a clock with a frequency half that of the internal clock is output from the PIXCLK pin. As a result, the PIXCLK pin can easily be directly connected to the OSD IC clock input pin, and the OSDSW pin can be directly connected to the BLK output pin. Thus, the BU1424K and the OSD IC can be synchronized, and OSD text with a burster trimmer stacker feature can be used. If the input data is in the RGB format, it is converted to YUV. If it is in the YUV format, it is converted from the CCIR-601 format to level-shifted YUV data. The YUV data is then adjusted to the 100IRE level in the NTSC, PAL, and PAL60 modes, and U and V data is phaseadjusted by a sub-carrier generated internally, and is modulated to chrominance signals. Ultimately, elements such as the necessary synchronization level, the color blanking level, and burst signals are mixed, and pass through the 9-bit DAC to be output as NTSC or PAL composite signals, luminance signals, and chrominance signals (conforming to RS170A). At this point, the DAC is operating at twice the internal clock, making it possible to reduce the number of attachments. Furthermore, luminance signal output and chrominance signal output can be turned off. At this point, it is possible to reduce the level of power consumption. The DAC output is current output. If a resistor of a specified value is connected to the IR pin, 2.0VP-P output can be obtained by connecting 75 to the VOUT pin as an external resistor. As a result, normally, when a video input pin (75 terminus) is connected, the output is approximately 1.0VP-P voltage output at a white 100% level. (2) Specifying the mode 1) Power saving mode With the BU1424K, setting the YCOFF pin to HIGH turns off the output from the YOUT and COUT pins of the DAC output, enabling use in the low power consumption mode.
Output mode and power consumption YOUT pin Luminance signal No output (0V) COUT pin Chrominance signal No output (0V) Power consumption (Typ.) 0.45W 0.25W
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Multimedia ICs
2) Output modes The "Video-CD" and "CD-G" modes can be supported by both digital image and video data, with the mode being switched by the CDGSWB pin input. When the CDGSWB pin input is LOW, the CD-G mode is set, and when HIGH, the Video-CD mode is set. Also, the "NTSC", "PAL", and "PAL60" modes may be selected Table 2: Specifying modes
NTB 0 0 1 1 1 1 PAL60 GDGSWB 0 1 0 1 0 1 Decoder mode CD-G Video-CD CD-G Video-CD CD-G Video-CD
BU1424K
as the output TV modes. The output TV mode is switched using the NTB and PAL60 pin input. Setting the NTB pin input to LOW sets the NTSC mode, and setting it HIGH with the PAL60 pin also HIGH sets the PAL mode. Setting the NTB pin HIGH and the PAL60 pin LOW, sets the PAL60 mode.
TV mode NTSC NTSC PAL60 PAL60 PAL PAL

0 0 1 1
Also, INT pin input can be used to switch between "interlace output" and "non-interlace output." Setting the input to LOW enables non-interlace output, and setting it to HIGH enables interlace output. When non-interlace output is used, the number of lines in one field can be controlled using the ADDH pin. If the Table 3: Pin settings for interlace / non-interlace modes
INT 0 0 1 ADDH 0 1 Scan Mode Non-interlace Non-interlace Interlace
ADDH pin is LOW, the number of lines in one field is set to the number of interlace output lines minus 0.5 lines, and when HIGH, the number of lines in one field is set to the number of interlace output lines plus 0.5 lines.
No. of Lines / Field NTSC / PAL60 262 263 262.5 PAL 312 313 312.5
3) Input formats The digital data input format can be set as shown in the table below, using the IM1 and IM0 pins. Both 24-bit Table 4: Input format settings
IM1 0 0 1 1 IM0 0 1 0 1
RGB (4: 4: 4) and 16-bit YUV (4: 2: 2) are supported. In addition, digital RGB input can be output as analog RGB output (RGB Through mode).
Input format R (8 bits), G (8 bits), B (8 bits) YUV16bit (4: 2: 2) -- ROSD, GOSD, BOSD expanded to RGB input
Output signal TV signals (9-bit resolution) TV signals (9-bit resolution) -- RGB analog signals (9 bits)
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Multimedia ICs
Table 5: Bit assignments in RGB Through mode
Output Pin YOUT (45) VOUT (39) COUT (37) BIT8 RD7 GD7 BD7 BIT7 RD6 GD6 BD6 BIT6 RD5 GD5 BD5 BIT5 RD4 GD4 BD4 BIT4 RD3 GD3 BD3 BIT3 RD2 GD2 BD2 BIT2 RD1 GD1 BD1
BU1424K
BIT1 RD0 GD0 BD0
BIT0 ROSD GOSD BOSD
The BU1424K has an internal OSD switch and chrominance data generating function. Consequently, joint usage of an OSD-IC with blanking and R, G, and B output can be easily supported by the OSD. Moreover, a clock with half the internal processing frequency of the BU1424K is output from the PIXCLK pin, and can be
connected to the OSD-IC clock input, enabling the timing to be captured. ROSD, GOSD, and BOSD pin input is effective as long as the OSDSW pin input is HIGH. The relationship between OSD data and chrominance data is as shown in Table 6 below.
Table 6: Correspondence between OSD function, input data and chrominance output
OSDSW 1 1 1 1 1 1 1 1 0 ROSD 0 0 0 0 1 1 1 1 GOSD 0 0 1 1 0 0 1 1 BOSD 0 1 0 1 0 1 0 1 Output chrominance signal Black (blanking) Blue Green Cyan Red Magenta Yellow White Based on input specified by IM0 and IM1
4) Clock modes With the BU1424K, clock input is available at the VCLK pin. Clocks supplied from an external source should basically be input at a frequency double that of clocks used internally (basic clock: BCLK) (when the CLKSW pin is LOW). The phase relationship between the internal clock and the external clock at this time is as shown in
HSY
Fig. 3, with the HSY pin input serving as a reference. In the Master mode, in which data from the HSY pin is output and used, HSY is output at the timing shown in Fig. 3. With the BU1424K, data (RD, GD, BD, etc.) is read at the rising edge of the internal clock (BCLK), so data should be input to the BU1424K as shown in Fig. 3.
VCLK
Internal clock (BCLK)
Input data
Fig.3
Illustration of clock timing (CLKSW is LOW)
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Multimedia ICs
Also, setting the CLKSW pin to HIGH enables the frequency of the external clock to be used as BCLK, the internal clock, just as it is. Since the data is read to the
HSY
BU1424K
BU1424K at the rising edge of BCLK at this time as well, data should be input as shown in Fig. 4. The relationship with HSY is also as shown in Fig. 4.
VCLK
Internal clock (BCLK)
Input data
Fig.4
Illustration of clock timing (CLKSW is HIGH)
With the BU1424K, the sub-carrier (burst) frequency is generated using the internal clock. For this reason, the Table 7: BU1424K clock input frequency settings
CLKSW pin 0 0 1 1 G4FSC pin 0 1 0 1
frequencies used in the various modes are limited, so those frequencies should be input (see Table 7 below).
Video-CD mode Same for NTSC / PAL / PAL60 27.000MHz 27.000MHz 13.500MHz 13.500MHz NTSC
CD-G mode PAL / PAL60 28.3750MHz 35.4695MHz 14.1875MHz 17.73475MHz
28.636MHz 28.636MHz 14.318MHz 14.318MHz
5) Synchronization signals The BU1424K has an "Encoder Master" mode in which synchronization signals are output, and an "Encoder Slave" mode in which synchronization signals are input from an external source and used to achieve synchronization. These modes are switched at the SLABEB pin. When the SLABEB pin is LOW, the Slave mode is in effect, and when HIGH, the Master mode is in effect. In the Master mode, the HSY and VSY pins serve as output, with horizontal synchronization signals (HSYNC) being output from the HSY pin and vertical synchronization signals (VSYNC) from the VSY pin. At this time, the reference timing for synchronization signal output is determined at the rising edge of the RSTB pin. Output is obtained in accordance with the specified mode (NTSC, PAL, or PAL60, interlace or non-interlace). Output in the non-interlace mode, however, is
output only under "Odd" field conditions (the falling edges of HSY and VSY are the same). In the Slave mode, the HSY and VSY pins serve as input, and horizontal synchronization signals (HSYNC) should be input to the HSY pin and vertical synchronization signals (VSYNC) to the VSY pin. The input synchronization signals at this time should be input in accordance with the specified mode. With the BU1424K, field distinction between odd and even fields is made automatically for each field when interlace input is used. With the BU1424K, all synchronization signals are treated as negative polarity signals (signals for which the sync interval goes LOW). When using the non-interlace mode, operation is normally carried out under odd field conditions (the falling edges of HSY and VSY are simultaneous).
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Multimedia ICs
6) Y filter With the BU1424K, the frequency characteristic of Y, which is mixed with the VOUT pin output, is set so that
BU1424K
it can be selected using the YFILON1 and 2 pins. A through filter is normally used on the YOUT pin output, so that it is not limited to this method.
Table 8: Frequency characteristic of the Y channel
YFILON2B H L H L YFILON1B H H L L Frequency characteristic of the Y channel TRAP filter through (same signal as YOUT pin output is mixed with VOUT) chart1 chart2 chart3
10 5 0 AMPLITUDE (dB) -5 - 10 - 15 - 20 - 25 - 30 - 35 - 40 100 1000 180 135 AMPLITUDE (dB) 90 PHASE (deg) 45 0 - 45 - 90 - 135 - 180 10000 20000
10 5 0 -5 - 10 - 15 - 20 - 25 - 30 - 35 - 40 100 1000 180 135 90 45 0 - 45 - 90 - 135 - 180 10000 20000 PHASE (deg)
FREQUENCY (kHz) CONT (c), END (e), COPY (Shift + Prt Sc)
FREQUENCY (kHz) CONT (c), END (e), COPY (Shift + Prt Sc)
Gain-Phase Graphic Fig.5 Chart1 (BCLK = 13.5MHz)
Gain-Phase Graphic Fig.6 Chart2 (BCLK = 13.5MHz)
10 5 0 AMPLITUDE (dB) -5 - 10 - 15 - 20 - 25 - 30 - 35 - 40 100 1000 180 135 90 45 0 - 45 - 90 - 135 - 180 10000 20000 PHASE (deg)
FREQUENCY (kHz) CONT (c), END (e), COPY (Shift + Prt Sc)
Gain-Phase Graphic Fig.7 Chart3 (BCLK = 14.318MHz)
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Multimedia ICs
BU1424K
(3) Output level Figures 8 to 10 indicate the digital data values for the DAC output when the color bars from the various pins are reproduced.
WHITE YELLOW CYAN GREEN MAGEN RED BLUE BLACK BLACK LEVEL = PEDESTAL LEVEL
SYNC TIP LEVEL
Fig.8 YOUT output
BLACK LEVEL
W H I T E
Y E L L O W
C Y A N
G R E E N
M A G E N T A
R E D
B L U E
B L A C K
COLOR BURST
Fig.9 COUT output
W H I T E
Y E L L O W
C Y A N
G R E E N
M A G E N T A
R E D
B L U E
BLACK LEVEL = PEDESTAL LEVEL
B L A C K
SYNC TIP LEVEL
Fig.10 VOUT output
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Multimedia ICs
Table 9: BU1424K color bar input / output data
Input (8-bit hexadecimal for each) RGB24bit RD -- -- -- -- 00 00 00 00 FF FF FF FF GD -- -- -- -- 00 00 FF FF 00 00 FF FF BD -- -- -- -- 00 FF 00 FF 00 FF 00 FF YUV (4: 2: 2) YD -- -- -- -- 10 28 90 A9 51 6A D2 EB UD -- -- -- -- 80 F1 36 A5 5A C9 0E 80 VD -- -- -- -- 80 6D 22 10 F0 DD 92 80 Output (9-bit hexadecimal for each) NAME&COLOR SYNC TIP Color Burst NTSC Color Burst PAL BLANK LEVEL BLACK (Pedestal) BLUE GREEN CYAN RED MAGENTA YELLOW WHITE VOUT is YOUT XXXH. YOUT 000 -- -- -- 072 092 117 138 0C6 0E6 16C 18C COUT -- 039 03D 100 000 064 085 08E 08E 085 064 000
BU1424K
VOUT 000 039 03D -- 072 064 085 08E 08E 085 064 000
COUT and VOUT display the chrominance amplitude. COUT is 100H XXXH.
(4) Timing Table 10 below shows the input and output pins related to timing. Table 10: BU1424K timing-related input / output pins
Pin No. 52 51 53 27 28 16 22 50 32 33 34 29 Pin name RSTB VCLK CLKSW VSY HSY CDGSWB NTB PAL60B INT SLABEB ADDH PIXCLK I/O I I I I/O I/O I I I I I I O System reset input pin Clock input pin
Function
Clock input mode setting pin Vertical synchronization signal I / O pin Horizontal synchronization signal I / O pin Video-CD / CD-G mode switching pin NTSC / PAL mode switching pin PAL / PAL60 mode switching pin Interlace / Non-interlace mode switching pin Master / Slave mode switching pin Pin which adds 1 line in non-interlace mode 1 / 2 divider output for internal clock (OSD clock)
1) Input clocks and input data timings in the various operation modes There are slight differences in the input data and the clock timing, depending on which mode is being used.
What is shared by all modes is that, with the BU1424K, data is read and discharged at the rising edge of the internal clock. The illustration below shows the input conditions in the various modes.
18
Multimedia ICs
1. Master mode, clock mode Encoder master (pin 33 = H) Internal clock = input clock (pin 53 = H)
VCLK (53pin)
BU1424K
BCLK (Internal clock)
Input data
Output data (HSY, VSY)
Tds1
Fig.11
In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise of the RSTB pin (pin 52). Table 11
Parameter Data setup time 1 Symbol Tds1 Min. 10 Typ. -- Max. --
2. Master mode, doubled clock mode Encoder master (pin 33 = H) Internal clock = 2 input clock (pin 53 = H)
VCLK (53pin)
BCLK (Internal clock)
Input data
Output data (HSY, VSY)
Tds2
Fig.12
In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, following the rise of the RSTB pin (pin 52). Table 12
Parameter Data setup time 2 Symbol Tds2 Min. 10 Typ. -- Max. --
19
Multimedia ICs
3. Slave mode, single clock mode Encoder slave (pin 33 = L) Internal clock = input clock (pin 53 = L)
BU1424K
VCLK (53pin)
BCLK (Internal clock)
Input data
output data (HSY, VSY)
Tds3
Tsh1
Tsd1
Fig.13
In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise of the RSTB pin (pin 52). Table 13
Parameter Data setup time 3 Sync signal hold time Sync signal hold time Symbol Tds3 Tsh1 Tsd1 Min. 10 10 10 Typ. -- -- -- Max. -- -- --
4. Slave mode, doubled clock mode Encoder slave (pin 33 = L) Internal clock = 2 input clock (pin 53 = L)
VCLK (53pin)
BCLK (Internal clock)
Input data
Input data (HSY, VSY)
Tds4
Tsh2
Tsd2
Fig.14
20
Multimedia ICs
BU1424K
In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, following the rise of the RSTB pin (pin 52). When HSY is input, phase correction is carried out at the falling edge, as shown in Fig. 14. (In other words, the phase of the internal clock (BCLK) is not determined until HSY is input.)
Table 14
Parameter Data setup time 4 Sync signal hold time 2 Sync signal setup time 2 Symbol Tds4 Tsh2 Tsd2 Min. 10 10 10 Typ. -- -- -- Max. -- -- --
BCLK (Internal clock)
HSY (IN / OUT)
PIXCLK
OSDSW
ROSD.GOSD
V,Y,C,OUT
VIDEO-DATA BLACK YELLOW VIDEO-DATA
Fig.15 Clock timing with the OSD function
The frequency of the PIXCLK pin output is one-half that of the internal clock. This phase is determined at the rising edge of HSY, as shown in Fig. 15. (In the Encoder Master mode, phase correction is implemented using the HSY output of the BU1424K itself.) The OSD function is effective only during the time that video output is enabled.
21
Multimedia ICs
2) Output timing 1. Master mode, doubled clock mode Encoder master (pin 33 = H) Internal clock = input clock 1 / 2 (pin 53 = L)
BU1424K
VCLK BCLK (Internal clock)
HSY (OUT) VSY (OUT)
Thdf Thdv
Thdr Tvdr
PIXCLK (OUT)
Tpdr
Fig.16 Output timing with a doubled clock
Table 15
Parameter HSY output delay VSY output delay PIXCLK output delay Symbol Thdr Thdf Tvdr Tvdf Tpdr Tpdf Min. -- -- -- Typ. 14 14 14 Max. -- -- --
2. Master mode, regular clock mode Encoder master (pin 33 = H) Internal clock = input clock (pin 53 = L)
VCLK BCLK (Internal clock)
HSY (OUT) VSY (OUT)
Thdf Tvdf
Thdr Tvdr
PIXCLK (OUT)
Tpdr
Fig.17 Output timing with a clock at the regular frequency
22
Multimedia ICs
Table 16
Parameter HSY output delay VSY output delay PIXCLK output delay Symbol Thdr Thdf Tvdr Tvdf Tpdr Tpdf Min. -- -- -- Typ. 10 10 10 Max. -- -- --
BU1424K
3) Odd / even recognition timing in Slave mode The BU1424K distinguishes whether the conditions of each field (each time that VSY is input) are odd or otherwise, and internal operation is carried out based on that recognition after the data is input. As a result, HSY and VSY are input under input conditions appropriate
to the specified mode, enabling regulated output for the first time. Odd input conditions are indicated below. Timing that does not match these conditions is recognized as an even field.
HSY
VSY
Tvl
Expanded view
HSY
VSY
Thvdiff
Fig.18 ODD recognition conditions
Table 17: Odd recognition conditions
Parameter VSY input L interval VSY Delay from HSY Symbol Tvl Thvdiff Min. 128 HSY falling edge - 1clk Typ. -- -- Max. -- HSY Rising edge - 2clk Unit BCLK BCLK
BCLK = One cycle of internal clock 23
Multimedia ICs
4) TV signal timing diagram
VOUT (39) BURST
BU1424K
BURST
YOUT (45)
COUT (37) Td1 Td2 Td3
BURST
BURST
Td4 Td5
Fig.19
Table 18
NTSC Parameter SYNC rise Burst start Burst end Data start 1-line interval Symbol Td1 Td2 Td3 Td4 Td5 Unit BCLK BCLK BCLK BCLK BCLK V-CD 64 71 106 128 858 CD-G 67 76 112 135 910 V-CD 64 76 106 142 864 PAL CDG2 83 100 140 186 1135 CDG1 67 79 112 149 908 V-CD 64 71 106 128 858 PAL60 CDG2 83 94 139 166 1127 CDG1 67 75 111 135 902
24
Multimedia ICs
Frame timing in Video-CD mode (NTSC / PAL60: Interlace)
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
12
18
19
20
Hsync (28pin)
Vsync (27pin) Odd_Field
VOUT (39pin)
Fig.20
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 281 282
259
Hsync (28pin)
Vsync (27pin) Even_Field
VOUT (39pin)
BU1424K
25
Frame timing in Video-CD mode (PAL: Interlace)
26
624 625 1 2 3 4 5 6 7 8 9 10 11 12 23 24 25
Multimedia ICs
623
Hsync (28pin)
Vsync (27pin) Odd_Field
VOUT (39pin)
Fig.21
311 312 313 314 315 316 317 318 319 320 321 322 323 324 335 336 337
310
Hsync (28pin)
Vsync (27pin) Even_Field
VOUT (39pin)
BU1424K
Multimedia ICs
Frame timing in CD-G mode (NTSC / PAL60: Non-interlace)
521
522
523
524
1
2
3
4
5
6
7
8
9
10
11
12
18
19
20
Hsync (28pin)
Vsync (27pin) First_Field
VOUT (39pin)
Fig.22
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 281 282
259
Hsync (28pin)
Vsync (27pin) Second_Field
VOUT (39pin)
BU1424K
27
Frame timing in CD-G mode (PAL: Non-interlace)
28
622 623 624 1 2 3 4 5 6 7 8 9 10 11 12 23 24 25
Multimedia ICs
Hsync (28pin)
Vsync (27pin) First_Field
VOUT (39pin)
Fig.23
310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 335 336 337
Hsync (28pin)
Vsync (27pin) Second_Field
VOUT (39pin)
BU1424K
Multimedia ICs
(5) Adjustment of the DAC output level The voltage level of the DAC output is determined by the DAC internal output current and the DAC output external resistor. The output current per 1 DAC bit is determined by the external resistor of the IR pin (pin 42), as shown below. I (1LSB) = VVREF / RIR 1 / 16 [A]****** (equation 6-1) VREF******Voltage generated by the regulator circuit in the BU1424K [V] RIR*********External resistor for the IR pin 1200 [] Consequently, when VREF = 1.3V and RIR = 1200, a
BU1424K
current of 67.71A per 1LSB is output. Because the white level of Y is a digital value of 396 (decimal value), the following results: V (Y white) = 0.0677 x 396 = 26.81[mA] At this point, if the DAC output external resistance is 37.5, an amplitude of 1.005[VP-P] is obtained. (6) YUV input mode With the BU1424K, setting the IM0 pin (pin 23) to HIGH enables a 16-bit YUV input format to be supported. At that time, the timing of U and V can be reversed when data is input, using the H / L state of the Test2 pin. The input conditions for this mode are shown below.
0 Internal clock (BCLK) HSY
1
2
2n 2n + 1
Y-Data
Y1
Y2
Y3
Y4
Y5
U.V-Data
U1
V1
U3
V3
U5
Fig.24 YUV input timing when TEST [2] = L
0 Internal clock (BCLK) HSY
1
2
2n 2n + 1
Y1
Y2
Y3
Y4
Y5
Y-Data
U1 V1 U3 V3 U5
U.V-Data
Fig.25 YUV input timing when TEST [2] = H
Reversal of the U and V timing using the H / L state of TEST[2] can be controlled regardless of whether CLKSW is HIGH or LOW (the input clock is a doubled clock or not).
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Multimedia ICs
BU1424K
When using the RGB input mode, TEST[2] should be fixed at LOW. In the Master mode, HSYNC is output at the timing shown on the previous page. For that reason, the timing of U and V should be determined by counting from that falling edge. In the Slave mode, the HSY, U, and V data should be input at the timing shown on the previous page.
Table 19
TEST2 (26pin) 0 0 1 1 CLKSW (53pin) 0 1 0 1 In a doubled clock mode, the timing of U and V is as shown in Fig. 24 In a regular clock mode, the timing of U and V is as shown in Fig. 24 In a doubled clock mode, the timing of U and V is as shown in Fig. 25 In a regular clock mode, the timing of U and V is as shown in Fig. 25
*External dimensions (Units: mm)
16.4 0.3 14.0 0.2 48 33 16.4 0.3 14.0 0.2 12.0 0.3 10.0 0.2 49 32 49 12.0 0.3 10.0 0.2 48 33 32
0.5
64 1 0.05 16
17
64 1 16
17
1.4 0.1
2.7 0.1
0.15 0.1
0.125 0.1
0.8
0.35 0.1 0.15
0.10
0.5
0.2 0.1 0.1
QFP-A64
VQFP64
30
0.5

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